1. Field of the Invention
This invention relates to a pattern forming method, and in particular to a resist pattern forming method including both a grating pattern, which is a fine pattern, and a pattern of arbitrary shape, in a lithography step in the course of a process of manufacturing a semiconductor device.
2. Description of the Background Art
The shrinking of semiconductor circuit patterns in recent years is largely attributable to the progress of optical lithography technique, which mainly results from wavelength shortening of an exposure light source. However, ways of shrinking patterns other than the wavelength shortening have been studied in many fields due to price increases in exposure device. For example, as a result of the progress such as enlargement of the aperture of a lens by scanner-type exposure technique, modified illumination technique, super-resolution mask technique or the like, there is a growing trend to shrink manufacturing dimensions of a pattern while maintaining an exposure wavelength. A reversed phenomenon has taken place from a 0.18 μm (180 nm) generation on down in which manufacturing dimensions are less than an exposure wavelength (KrF Excimer laser: 248 nm).
In forming a fine pattern less than the wavelength of light that is used for exposure, techniques using a half-tone phase shift mask, a phase shift mask, and a modified illumination technique are well known. In techniques using the masks, a special mask is used having a portion thereon for inverting the phase of light of an exposure wavelength, for example, to enhance optical intensity contrast on an image-forming surface by an optical interference effect.
In the modified illumination technique, a mask surface is illuminated by optimizing the shape of illumination such that all complicated circuit patterns designed on the mask are formed with stability in dimensions and two-dimensional shapes thereof, to enhance optical intensity contrast of all the patterns on an image-forming surface.
For example, with a fine circuit pattern that includes a pattern (grating pattern (repetition pattern)) in a lattice having fine lines and spaces being repeated alternately, and a pattern (standard pattern) provided to be partly continuous with the grating pattern and to have larger dimensions than the grating pattern, the shape of illumination has been optimized such that excellent optical contrast is obtained for the fine circuit pattern.
A typical example is the optimization of an outer contour radius (outer diameter R1) and an inner contour radius (inner diameter R2) of annular illumination that blocks light circularly at the center of an illumination optical system. The sizes of four openings of four-lens illumination have been optimized as well.
U.S. Pat. No. 5,858,580 discloses forming a fine circuit pattern by a two-exposure process, in which a wiring portion thinner than an exposure wavelength is formed using a phase shift mask and the other portions are formed using a standard mask. This method is being put to practically use.
In addition, U.S. Pat. No. 5,415,835 and Japanese Patent Application Laid-Open No. 2000-349010 disclose forming a fine circuit pattern by a multiple exposure process including a two-exposure process. U.S. Pat. No. 5,415,835 discloses a technique of fabricating a fine pattern by performing a dual beam interference exposure with a device other than standard reduced projection exposure devices. Further, U.S. Pat. No. 5,858,580, Japanese Patent Application Laid-Open No. 2000-349010, U.S. Pat. Nos. 6,228,539, 6,258,493 and 6,566,023, and United States Patent Application Publication No. 2004-197680 disclose a method in which a standard exposure step and a fine isolated wiring pattern (gate pattern) or fine periodic pattern exposure step are performed without intervention of a development process, the fine isolated wiring pattern or fine periodic pattern exposure step being performed using a Levenson type phase shift mask (Alternative Phase Shift Mask) in which phase-inverted complete transmissive areas are juxtaposed to each other. Furthermore, International Patent Application Publication No. WO99/65066 and Japanese Patent Application Laid-Open No. 2000-021718 disclose a method of forming a periodic pattern using dipole illumination, and forming an isolated pattern by erasing the periodic pattern other than a partial wiring in the periodic pattern with a standard pattern by means of exposure.
The following equation (1) is the Rayleigh equation indicative of optical resolution:R=k1·(λ/NA)   (1)where R is pattern resolution, λ is an exposure wavelength, NA is a lens numerical aperture, and k1 is a process factor.
It is now assumed that a resist pattern for a fine circuit pattern that includes a grating pattern having a process factor k1 of less than “0.3”, and a standard pattern having an arbitrary pattern such as fine isolated space and a process factor k1 of “0.5” level, is subjected to patterning. It may be required in some instances that a grating pattern and standard pattern be connected in such resist pattern.
In the conventional techniques described above, it is difficult to resolve this fine circuit pattern with stability no matter how optimized the shape of illumination is. For example, setting the NA to “0.85” with the ArF wavelength (193 nm), the grating pattern of 65 nm L/S will have a process factor k1 of “0.28”. In this case, it was extremely difficult even with a phase shift mask technique having a process factor k1 of less than “0.3” to form the fine circuit pattern with high accuracy that includes the fine grating pattern and the arbitrary standard pattern having a process factor k1 of “0.5” level.
This is because when a phase shift mask suitable for the grating pattern is used, a phase mismatch associated with the principle of phase shift mask occurs inevitably due to the pattern arbitrariness, leaving an unintentional and unnecessary pattern on the standard pattern side. Although a negative type resist is commonly used in order to avoid this problem, a resist material having excellent resolution characteristics for the ArF wavelength is nonexistent, and if it does exist, then the resolution between the same phases will inevitably be insufficient due to the circuit structure.